J. Obert
Sandia National Labs,
United States
Keywords: VLSI static analysis, VLSI dynamic analysis, semi-supervised learning, reinforcement learning
Summary:
To counter manufacturing irregularities and ensure ASIC design integrity, it is essential that robust design verification methods are employed. It is possible to ensure such integrity using ASIC static timing analysis (STA) and machine learning. In this presentation uniquely devised machine and statistical learning methods which quantify anomalous variations in Register Transfer Level (RTL) or Graphic Design System II (GDSII) formats are discussed. To measure the variations in ASIC analysis data, the timing delays in relation to path electrical characteristics are explored. It will be shown that semi-supervised learning techniques are powerful tools in characterizing variations within STA path data and has much potential for identifying anomalies in ASIC RTL and GDSII design data. Also discussed is a strategy using reinforcement learning (RL) for optimally reducing dynamic timing analysis resources, and fully verifying VLSI chip design and functionality.