Towards Secure DoD Hardware: Device with Secure Interconnect and Enhanced Resilience Against Hardware Trojans and Side-Channel Attacks

A. Ganguly and S. Manoj
George Mason University, United States

Keywords: Hardware security, communication, machine learning, side-channel attacks, IP protection

We propose to equip the on-chip interconnect with a secure engine called Unified Attack Monitoring Unit, for both Hardware Trojan (HT) detection and Side-Channel Attack (SCA) resilience for current and future scalable systems. Towards active HT detection resulting from malicious design or IP cloning intentions, the power supply to the voltage islands can be monitored and any unauthorized activity in the cores of specific islands can be sensed and detected. Similarly, towards a passive HT detection, the secure unit grants access to the on-chip interconnect in a scrambled sequence known only to the secure unit. Therefore, any unauthorized access of the bus due to embedded trojan can be sensed by the Bus Sensing unit and result in an attack detection. Following an attack detection, specific IPs can be either barred from accessing the interconnect by reconfiguring the Bus Access Arbiter or powered down to eliminate suspicious or unauthorized activities. For an enhanced resilience against SCAs, the SCA attack detection is performed by analyzing the energy consumption and the microarchitectural event (obtained through Hardware Performance Counters (HPCs)) analysis for a given test vector from the secure engine. This aids in detecting passive as well as active SCAs.