S. Seo, S. Kim
University of Rhode Island, Rhode Island, United States
Keywords: Synthetic Aperture Radar, Onboard processing, ASIC, Heterogeneous
Challenges for the onboard real-time processing of the large-scale synthetic aperture radar (SAR) include the large data storage and significant computing resources. These challenges become more serious when it comes to space instruments with SWaP-C constraints, for example, CubeSats. A compact, energy-efficient chip solution for the onboard real-time SAR processor will be developed by utilizing a heterogenous computing architecture. The core elements, our new Fast Fourier Transform (FFT) and Inverse FFT (IFFT) accelerators, in the SAR processing will be implemented using in-memory techniques and the remaining elements will be implemented using conventional logic computing techniques. Single precision FFT/IFFT accelerators will be first developed using in-memory techniques and then they will be integrated with a conventional logic computing engine into a single chip toward the heterogeneous SAR processor, featuring a compact form factor, high energy efficiency, and minimum storage requirement. The chip solution will be developed specifically for space-borne SAR satellites, but it can find applications in other military applications as well, for example, tactical intelligence, surveillance, target acquisition and reconnaissance in harsh environments (cloud, fog, haze, smoke, etc.). The proposed solution also can be used for ground moving target indicators, which are detecting moving vehicles, troops, or aircraft.